1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically, it relates to a semiconductor memory device having a split hierarchical power supply structure.
2. Description of the Prior Art
(1) Prior Art 1
In a recent CMOS semiconductor integrated circuit device, a device such as a MOS transistor is now being refined while the power supply voltage therefor is reduced in order to improve the reliability of the refined device and reduce power consumption. The threshold voltage Vth of the MOS transistor is also reduced for performing a high-speed operation with the low power supply voltage.
If the threshold voltage Vth of the MOS transistor is reduced, however, a subthreshold leakage current flowing between its source and drain is increased when the MOS transistor is non-conductive. This leads to increase of the direct current consumed by the overall CMOS semiconductor integrated circuit device, particularly in a standby state. In order to solve this problem, an MT-CMOS (multi-threshold CMOS) system has been proposed.
FIG. 60 is a circuit diagram showing a principal part of a CMOS semiconductor integrated circuit device employing the MT-CMOS system. Referring to FIG. 60, the CMOS semiconductor integrated circuit device includes a CMOS logic circuit (invertor)INV in FIG. 60) formed by a P-channel MOS transistor QP1 and an N-channel MOS transistor QN1 having low threshold voltages LVthp and LVthn respectively and a P-channel MOS transistor QP2 having a relatively high threshold voltage MVthp.
The P-channel MOS transistor QP1 and the N-channel MOS transistor QN1 are serially connected between a power supply node N1 and a ground node N2 of the invertor INV while the gates thereof are connected to an input node N3 of the invertor INV and the drains thereof form an output node N4 of the invertor INV. The P-channel MOS transistor QP2 is connected between a line of a power supply potential Vcc and the power supply node N1 of the inverter INV, and its receives a chip selection signal /CS. The ground node N2 of the invertor INV is connected to a line of a ground potential GND.
In an active state, the signal /CS goes low for activation and the P-channel MOS transistor QP2 is rendered conductive for supplying the power supply potential Vcc to the power supply node N1 of the invertor INV. When an input signal VI for the invertor INV falls from a high level to a low level, the P-channel MOS transistor QP1 is rendered conductive and the N-channel MOS transistor QN1 is rendered non-conductive so that an output signal VO from the invertor INV goes high. At this time, a high-speed operation is attained due to the low threshold voltages LVthp and LVthn of the P-channel MOS transistor QP1 and the N-channel MOS transistor QN1.
In a standby state, the signal /CS goes high for inactivation and the P-channel MOS transistor QP2 is rendered non-conductive for stopping the supply of the power supply potential Vcc to the power supply node N1 of the invertor INV. The input signal VI rises from the low level to a high level, the P-channel MOS transistor QP1 is rendered non-conductive and the N-channel MOS transistor QN1 is rendered conductive so that the output signal VO goes high. While a subthreshold leakage current flows from the line of the power supply potential Vcc to the line of the ground potential GND through the MOS transistors QP2, QP1 and QN1 at this time, this subthreshold leakage current is suppressed low due to the presence of the P-channel MOS transistor QP2 having the relatively high threshold voltage MVthp.
(2) Prior Art 2
When the threshold value of a transistor is reduced following refinement of the transistor and reduction of a power supply voltage, the value of a subthreshold current flowing in an OFF state of the transistor is increased. Japanese Patent Laying-Open No. 6-237164 (1994) discloses an SCRC (subthreshold current reduction control) technique for reducing such a subthreshold current. According to this SCRC technique, switches are inserted between a CMOS invertor circuit and a power source and between the CMOS invertor circuit and the ground respectively. In an active state, both switches are turned on so that the invertor circuit supplies an output signal in response to an input signal as general. When the invertor circuit supplies an output signal of a high logical level in a standby state, the switch for the power source is turned on while that for the ground is turned off.
A subthreshold current flowing through an N-channel MOS transistor provided in the invertor circuit is reduced since the switch for the ground is turned off. When the invertor circuit supplies an output signal of a low logical level in the standby state, on the other hand, the switch for the power source is turned off and that for the ground is turned on. In this case, a subthreshold current flowing through a P-channel MOS transistor provided in the invertor circuit is reduced since the switch for the power source is turned off.
Japanese Patent Laying-Open No. 6-203558 (1994) discloses a dynamic random access memory (DRAM) employing the aforementioned SCRC technique. In this DRAM, a word line driver is split into blocks, so that each block is provided with a plurality of word line drivers and a sub power supply line connected to these word line drivers in common. Each sub power supply line is connected to a main power supply line in common through a selection transistor. Each selection transistor is turned on when the corresponding block is in an active state, and turned off when in a standby state. In a block of a standby state, therefore, subthreshold currents flowing through the word line drivers are reduced.
(3) Prior Art 3
FIG. 61 is a circuit diagram showing a principal part of a CMOS semiconductor integrated circuit device employing the so-called hierarchical power supply system. Referring to FIG. 61, the CMOS semiconductor integrated circuit device includes main power supply lines ML, main ground lines ML', a sub power supply line SL, a sub ground line SL', a P-channel MOS transistor QP5, an N-channel MOS transistor QN5 and a plurality of invertors INV1, INV2, . . . The P-channel MOS transistor QP5 and the N-channel MOS transistor QN5 have relatively high threshold voltages MVthp and MVthn respectively. The invertors INV1, INV2, . . . are formed by P-channel MOS transistors and N-channel MOS transistors having relatively low threshold voltages LVthp and LVthn respectively, similarly to the invertor INV shown in FIG. 60.
Each main power supply line ML is externally supplied with a power supply potential Vcc. The P-channel MOS transistor QP5 is connected between the main power supply line ML and the sub power supply line SL, and its gate receives an inverted signal /.phi.a of an activation signal .phi.a.
Each main ground line ML' is externally supplied with a ground potential GND. The N-channel MOS transistor Qn5 is connected between the main ground line ML' and the sub ground line SL', and its gate receives the activation signal .phi.a.
As shown in FIGS. 62A and 62B, the activation signal .phi.a goes low in a standby state and high in an active state. The MOS transistors QP5 and QN5 are turned off in the standby state to disconnect the sub power supply line SL and the sub ground line SL' from the main power supply line ML and the main ground line ML' respectively, while the MOS transistors QP5 and QN5 are turned on in the active state to connect the sub power supply line SL and the sub ground line SL' to the main power supply line ML and the main ground line ML' respectively.
The invertors INV1, INV2, . . . are serially connected with each other. A signal VI is inputted in the initial-stagelinvertov INV1. The signal VI goes low in the standby state and high in the active state.
Power supply nodes of the odd-stage invertor INV1, INV3, . . . whose P-channel MOS transistors are rendered conductive in the standby state to output high levels are connected to the main power supply lines ML, and ground nodes thereof are connected to the sub ground line SL'.
Power supply nodes of the even-stage invertors INV2, INV4, . . . whose N-channel MOS transistors are rendered conductive in the standby state to output low levels are connected to the sub power supply line SL and ground nodes thereof are connected to the main ground lines ML'.
In the standby state, the main power supply lines ML and the main ground lines ML' are disconnected from the sub power supply line SL and the sub ground line SL' respectively, to reduce standby currents, i.e., subthreshold leakage currents of the MOS transistors included in the invertors INV1, INV2, . . . At this time, the outputs of the invertors INV1, NV2, . . . are not unstabilized since the power supply nodes of the invertors INV1, INV3, . . . outputting high levels are connected to the main power supply lines ML while the ground nodes of the invertors INV2, INV4, . . . outputting low levels are connected to the main ground lines SL.
In the active state, the main power supply lines ML and the main ground lines ML' are connected with the sub power supply line SL and the sub ground line SL' respectively, to supply the invertor NV1, INV2, . . . with the power supply potential Vcc and the ground potential GND. The invertors INV1, INV2, . . . , which are formed by the P-channel MOS transistors and the N-channel MOS transistors having the relatively low threshold voltages LVthp and LVthn respectively, operate at a high speed.
However, the CMOS semiconductor integrated circuit device shown in FIG. 60 regularly renders the P-channel MOS transistor QP2 conductive in the active state even if the invertor INV may not be supplied with the power supply potential Vcc (the signal VI is at a high level), and still consumes a large current.
Although the SCRC technique can reduce a subthreshold current flowing in a standby state as described above, the voltage of a sub power supply line, electrically disconnected from a main power supply line in the standby state, remarkably lowers from a power supply voltage in the standby state. While the sub power supply line is connected to the main power supply line when the standby state is converted to an active state, a prescribed time is required for the voltage of the sub power supply line to reach the power supply voltage. Immediately after entering the active state, therefore, a logic circuit connected to the sub power supply line cannot correctly operate.
Japanese Patent Laying-Open No. 8-83487 (1996) discloses a method for solving this problem. According to this method, a voltage set circuit is provided for setting the voltage of a main power supply line at a prescribed level lower than a power supply voltage. However, this voltage set circuit operates not only in a standby state but also in an active state, and hence consumes large current.
In the CMOS semiconductor integrated circuit shown in FIG. 61, the sub power supply line SL and the sub ground line SL' require a certain degree of time for reaching the power supply potential Vcc and the ground potential GND after the MOS transistors QP5 and QN5 are turned on in a first active cycle after power supply, and hence the circuit operation is disadvantageously retarded to cause a malfunction.